Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks

Tiantian Liu; Minming Li; Chun Jason Xue

doi:10.1109/ASPDAC.2010.5419909

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks

Tiantian Liu^*
, Minming Li
, Chun Jason Xue

^*Corresponding author for this work

City University of Hong Kong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and minimizing runtime overhead are two objectives investigated in this paper. Experiments show that the algorithms proposed can reduce the overhead caused by BSLs efficiently.

Original language	English
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages	113-118
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419909
State	Published - 2010
Externally published	Yes
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China Duration: 18 Jan 2010 → 21 Jan 2010

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country/Territory	Taiwan, Province of China
City	Taipei
Period	18/01/10 → 21/01/10

Access to Document

10.1109/ASPDAC.2010.5419909

Cite this

Liu, T., Li, M., & Xue, C. J. (2010). Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 113-118). Article 5419909 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419909

@inproceedings{7a365c9d8efa4c12a81de20bd5371003,

title = "Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks",

abstract = "Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and minimizing runtime overhead are two objectives investigated in this paper. Experiments show that the algorithms proposed can reduce the overhead caused by BSLs efficiently.",

author = "Tiantian Liu and Minming Li and Xue, \{Chun Jason\}",

year = "2010",

doi = "10.1109/ASPDAC.2010.5419909",

language = "英语",

isbn = "9781424457656",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "113--118",

booktitle = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010",

note = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 18-01-2010 Through 21-01-2010",

}

Liu, T, Li, M & Xue, CJ 2010, Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419909, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 113-118, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 18/01/10. https://doi.org/10.1109/ASPDAC.2010.5419909

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. / Liu, Tiantian; Li, Minming; Xue, Chun Jason.
2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 113-118 5419909 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Minming

AU - Xue, Chun Jason

PY - 2010

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N2 - Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and minimizing runtime overhead are two objectives investigated in this paper. Experiments show that the algorithms proposed can reduce the overhead caused by BSLs efficiently.

AB - Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and minimizing runtime overhead are two objectives investigated in this paper. Experiments show that the algorithms proposed can reduce the overhead caused by BSLs efficiently.

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T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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Y2 - 18 January 2010 through 21 January 2010

ER -

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks

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