TY - GEN
T1 - Orientation controlled GaSb nanowires
T2 - 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018
AU - Yang, Zaixing
AU - Ho, Johnny C.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/5
Y1 - 2018/12/5
N2 - In recent years, high-mobility GaSb nanowires have received tremendous attention for high-performance p-type transistors; however, due to the difficulty in achieving thin, uniform and orientation-controlled nanowires (NWs), there is limited report until now addressing their orientation-dependent properties in this important one-dimensional material system, where all these are essential information for the deployment of GaSb NWs in various applications. Using CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility 〈111〉 -oriented GaSb nanowires (NWs) via vapor-solid-solid (VSS) growth by the newly developed surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor-liquid-solid (VLS) mechanism, cylindrical-shaped Pd 5 Ga 4 catalytic seeds were present in our Pd-catalyzed VSS-NWs. As solid catalysts, stoichiometric Pd 5 Ga 4 was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface orientation at the seed/NW interface for efficient epitaxial NW nucleation. Over 95% high crystalline quality NWs were grown in 〈111〉 orientation for a wide diameter range of between 10 and 70 nm. Back-gated field-effect transistors (FETs) fabricated using the Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of 330 cm 2 V -1 s -1 , close to the mobility limit for a NW channel diameter of 30 nm with a free carrier concentration of 10 18 cm -3 . This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, surface morphology and electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.
AB - In recent years, high-mobility GaSb nanowires have received tremendous attention for high-performance p-type transistors; however, due to the difficulty in achieving thin, uniform and orientation-controlled nanowires (NWs), there is limited report until now addressing their orientation-dependent properties in this important one-dimensional material system, where all these are essential information for the deployment of GaSb NWs in various applications. Using CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility 〈111〉 -oriented GaSb nanowires (NWs) via vapor-solid-solid (VSS) growth by the newly developed surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor-liquid-solid (VLS) mechanism, cylindrical-shaped Pd 5 Ga 4 catalytic seeds were present in our Pd-catalyzed VSS-NWs. As solid catalysts, stoichiometric Pd 5 Ga 4 was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface orientation at the seed/NW interface for efficient epitaxial NW nucleation. Over 95% high crystalline quality NWs were grown in 〈111〉 orientation for a wide diameter range of between 10 and 70 nm. Back-gated field-effect transistors (FETs) fabricated using the Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of 330 cm 2 V -1 s -1 , close to the mobility limit for a NW channel diameter of 30 nm with a free carrier concentration of 10 18 cm -3 . This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, surface morphology and electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.
UR - https://www.scopus.com/pages/publications/85060310554
U2 - 10.1109/ICSICT.2018.8565764
DO - 10.1109/ICSICT.2018.8565764
M3 - 会议稿件
AN - SCOPUS:85060310554
T3 - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
BT - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
A2 - Tang, Ting-Ao
A2 - Ye, Fan
A2 - Jiang, Yu-Long
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 31 October 2018 through 3 November 2018
ER -